As an SOI wafer for a RF (Radio Frequency) device, the SOI wafer has been treated by increasing the resistivity of the base wafer. However, it has been required to cope with higher frequency in order to handle further speedup, and accordingly it comes to be difficult to handle only by using conventional high-resistance wafers.
Hence, it is suggested as measures that a layer, which is effective in annihilating generated carriers (a carrier trap layer), should be added immediately under a buried oxide film layer (a BOX layer) of an SOI wafer. It is becoming necessary to form a polycrystalline silicon layer having high resistivity on a base wafer to recombine carriers generated in the high-resistivity wafer.
Patent Document 1 describes forming a polycrystalline silicon layer or an amorphous silicon layer as the carrier trap layer at an interface between a BOX layer and a base wafer. On the other hand, Patent Document 2 also describes forming a polycrystalline layer as the carrier trap layer at an interface between a BOX layer and a base wafer; furthermore, heat treatment temperature after forming the polycrystalline silicon layer is restricted to prevent recrystallization of the polycrystalline silicon layer.
Moreover, Patent Document 3 describes forming a dielectric material layer of thickness of 0.5 to 10 nm, which is different from a native oxide film, on a silicon substrate having a high resistivity more than 500 Ω·cm, and then forming a polycrystalline silicon layer to manufacture an SOI wafer usable for RF devices.
Meanwhile, Patent Document 4 describes forming a polycrystalline silicon layer or an amorphous silicon layer on a bonding surface side of a base wafer; further, the base wafer used has a resistivity of 100 Ω·cm or more and the surface, on which the polycrystalline silicon layer is formed, has a surface roughness of 2 nm or more.
In addition, Patent Document 5 describes forming a thermal nitride film on a bonding surface side of a base wafer having a resistivity of 100 Ω·cm or more before a step of forming a polycrystalline silicon layer or an amorphous silicon layer on the bonding surface side of the base wafer.